The present invention relates to a capacitor, and a semiconductor device comprising the capacitor, more specifically to a capacitor using a dielectric thin film, and a semiconductor device comprising the capacitor.
The present invention also relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device which can ensure stable operation in high frequency region, and a method for fabricating the semiconductor device.
Generally, a decoupling capacitor is mounted near an LSI (Large Scale Integrated Circuit), etc. mounted on a circuit wiring substrate, for the prevention of erroneous operation due to source voltage variations and high frequency noises.
The substrate of the decoupling capacitor is independent of the circuit wiring substrate and is suitably mounted on the circuit wiring substrate.
Recently, as LSIs, etc. have higher speed and lower power consumption, the decoupling capacitor is required to have characteristics improved. As LSIs, etc. are more down-sized, the decoupling capacitor is required to be down-sized.
Then, techniques of increasing capacitances while satisfying the requirement of down-sizing the decoupling capacitor have been proposed.
A proposed capacitor will be explained with reference to FIG. 36. FIG. 36 is a sectional view of the proposed capacitor.
As shown in FIG. 36, a conducting film 312 formed of a 50 nm-thickness Ti film and a 200 nm-thickness Pt film laid the latter on the former is formed on a silicon substrate 310. On the conducting film 312, a 200 nm-thickness dielectric film 314 of BST ((Ba,Sr)TiO3), which is highly dielectric, is formed.
On the dielectric film 314, a conducting film 318 of a 200 nm-thickness Pt film is formed. On the conducting film 318, a dielectric film 322 is formed of a 200 nm-thickness BST film. The conducting film 322 is formed, covering the conducting film 318.
On the dielectric film 322, a conducting film 334 is formed of a 200 nm-thickness Pt film, connected to the conducting film 312 through an opening 324.
Further on the entire surface, a passivation film 338 of polyimide is formed. In the passivation film 338, a contact hole 340 and a contact hole 342 are formed respectively down to the conducting film 334 and the conducting film 318.
A conducting film 344 is formed on the inside surfaces of the contact holes 340, 342. Conductor plugs 346a, 346b of Pt are buried respectively in the contact holes 340, 342 with the conducting film 344 formed on the inside surfaces. Solder bumps 348a, 348b are formed respectively on the conductor plugs 346a, 346b. 
The conducting film 312 and the conducting film 334 form a first electrode 350 of the capacitor. The first electrode 350 is electrically connected to electric source lines of, e.g., circuit wiring substrate (not shown) through the conductor plug 346a and the solder bump 348a, etc.
The conducting film 318 forms a second electrode 352 of the capacitor. The second electrode 352 is electrically connected to ground lines of, e.g., the circuit wiring substrate (now shown) through the conductor plug 346b, and the solder bump 348b, etc. The proposed capacitor 354 is thus formed.
In the capacitor shown in FIG. 36, a material of the dielectric films 314, 322 is BST, which is dielectric, and the dielectric films 314, 322 are as thin as 200 nm. The capacitor can have improve capacitances. Furthermore, in the capacitor shown in FIG. 36, the conducting films 312, 334 forming the first electrode 350 is formed are formed below and above the conducting film 318 forming the second electrode 352 respectively with the dielectric films 314, 322 intervening. Thus, the capacitor can increase capacitances while satisfying the requirement of down-sizing.
However, the capacitor shown in FIG. 36 has the voltage resistance lowered. Reasons for the lower voltage resistance have not been made clear, and the lower voltage resistance has been a barrier to practicing the proposed capacitor.
Recently, digital LSIs, etc., typically microprocessors, have the operation speed increased and the electric power consumption decreased.
In order to operate an LSI in a high frequency region of the GHz band and at low voltages, it is very important that source voltage variations due to abrupt load impedance variations of the LSI are depressed, and high frequency noises of the electric sources are removed.
Conventionally, the decoupling capacitor is mounted near an LSI or others mounted on a circuit wiring substrate, whereby source voltage variations are depressed, and high frequency noises are removed. The decoupling capacitor is formed on a substrate independent of the circuit wiring substrate and is suitably mounted on the circuit wiring substrate.
In mounting the decoupling capacitor near an LSI mounted on a circuit wiring substrate, the LSI and the decoupling capacitor are electrically connected through the wire formed on the circuit wiring substrate, and large inductance due to the wiring is present. When large inductance is present between the LSI and the decoupling capacitor, source voltage variations cannot be sufficiently depressed, and high frequency noises cannot be sufficiently removed.
Here, in order to shorten the wring between the LSI and decoupling capacitor, it is proposed to mount the decoupling capacitor directly on the LSI. Mounting the decoupling capacitor directly on the LSI will be able to decrease inductance between the LSI and the decoupling capacitor.
However, in simply mounting the decoupling capacitor directly on the LSI, the decoupling capacitor will be a barrier to flip chip bonding, which is advantageous for high speed operation.
The specification of Japanese Patent Laid-Open Publication No. Hei 9-223861/1997 discloses a technique of mounting a semiconductor chip on the surface of a circuit wiring substrate, mounting the decoupling capacitor on the back side of the circuit wiring substrate, and electrically connecting the semiconductor chip and the decoupling capacitor through a via formed in the circuit wiring substrate. However, some inductance is present due to the via formed in the circuit wiring substrate, whereby source voltage variations cannot be depressed sufficiently, and high frequency noises cannot be removed sufficiently.
The specification of Japanese Patent Laid-Open Publication No. Hei 5-102389/1993 discloses a technique of mounting the decoupling capacitor on a memory IC. A long wiring pattern is present between the source pins and ground pins of the memory IC, and the decoupling capacitor, which makes it impossible to sufficiently depress source voltage variations and to remove high frequency noises.
The specification of Japanese Patent Laid-Open Publication No. Hei 9-64236/1997 discloses a technique of mounting the decoupling capacitor directly on a semiconductor chip. However, the decoupling capacitor has a very large thickness, and is not able to satisfy the requirements of down-sizing and higher density.
In order to improve operation speed, further it is very important that the wiring between the decoupling capacitor and an LSI is short, and also the wiring between the LSI and the other passive members, such as resistors, inductors, etc., is short. To this end, a technique of shortening not only the wiring between the decoupling capacitor and an LSI, but also the wiring between passive devices other than the decoupling capacitor and the LSI has been needed.